fqd12n20 l tm_f085 200v logic level n-channel mosfet fqd12n20 ltm_f085 200v logic level n-channel mosfet genera l description these n -channel enhancement mode power field effect transistors are produced using fairchild?s proprietary, planar stripe, dmos technology. this advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. these devices are well suited for high efficiency switching dc/dc converters, switch mode power supply, motor control. featur es 9.0 a, 200v, r ds(on) = 0.28 ? @v gs = 10 v low gat e charge ( typical 16 nc) low crss ( typical 17 pf) fast switching 100% avalanche tested improved dv/dt capability low level gate drive requirement allowing direct opration from logic drivers absolu te maximum ratings t c = 25c unless otherwise noted ther mal characteristics symbol paramet er FQD12N20LTM_f085 units v dss drain-source vo ltage 200 v i d drain current - cont inuous (t c = 25c) 9.0 a - cont inuous (t c = 100c) 5.7 a i dm drain current - p ulsed (note 1) 36 a v gss gate -source voltage 20 v i ar avalanche current (note 1) 9.0 a dv/dt peak diode recovery dv/dt (note 2) 5.5 v/ns p d power dissipation (t a = 25c) * 2.5 w power dissipation (t c = 25c) 55 w - de rate above 25c 0.44 w/c t j , t stg operating and storage temperature range -55 to +150 c t l maximum lead t emperature for soldering purposes, 1/8 " from case for 5 seconds 300 c symbol parameter typ max units r jc thermal re sistance, junction-to-case -- 2.27 c / w r ja thermal re sistance, junction-to-ambient * -- 50 c / w r ja thermal re sistance, junction-to-ambient -- 110 c / w * when mo unted on the minimum pad size recommended (pcb mount) d-pak g s d ? rohs compliant june 2010 ? qualified to aec q101 ! " ! ! ! " " " ! " ! ! ! " " " ?2010 fair child semiconductor corporation 1 www.fairchildsemi.com FQD12N20LTM_f085 rev. b
fqd12n20 ltm_f085 200v logic level n-channel mosfet (note 3) (note 3, 4) (note 3, 4) (note 3) electrical characteristics t c = 25c unless otherwise noted notes: 1. repetitive rating : pulse width limited by maximum junction temperature 2. i sd 11.6a, di/dt 300a/ s, v dd bv dss, starting t j = 25c 3. pulse test : pulse width 300 s, duty cycle 2% 4. essentially independent of operating temperature symbol parameter test conditions min typ max units off ch aracteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a 200 -- -- v ? bv dss / ? t j breakdown vol tage temperature coefficient i d = 250 a, referenced to 25c -- 0.14 -- v/c i dss zero ga te voltage drain current v ds = 200 v, v gs = 0 v -- -- 1 a v ds = 160 v, t c = 125c -- -- 1 0 a i gssf gate -body leakage current, forward v gs = 20 v, v ds = 0 v -- -- 100 na i gssr gate -body leakage current, reverse v gs = -20 v, v ds = 0 v -- -- -100 na on chara cteristics v gs(th ) gate threshold v oltage v ds = v gs , i d = 250 a 1.0 -- 2.0 v r ds(on) static drain-s ource on-resistance v gs = 10 v, i d = 4.5 a v gs = 5 v, i d = 4.5 a -- 0. 22 0.25 0.28 0.32 ? g fs forward transconductance v ds = 30 v, i d = 4.5 a -- 11.6 -- s dynamic ch aracteristics c iss inpu t capacitance v ds = 25 v, v gs = 0 v, f = 1.0 mhz -- 830 1080 pf c oss output c apacitance -- 120 155 pf c rss reverse tr ansfer capacitance -- 17 22 pf switchin g characteristics t d(on) turn-o n delay time v dd = 100 v, i d = 11.6 a, r g = 25 ? -- 15 40 ns t r turn-o n rise time -- 190 390 ns t d(off) turn -off delay time -- 60 130 ns t f turn -off fall time -- 120 250 ns q g total ga te charge v ds = 160 v, i d = 11.6 a, v gs = 5 v -- 16 21 nc q gs gate -source charge -- 2.8 -- nc q gd gate -drain charge -- 7.6 -- nc drain -source diode characteristics and maximum ratings i s maximum cont inuous drain-source diode forward current -- -- 9.0 a i sm maximum p ulsed drain-source diode forward current -- -- 36 a v sd drain-source diode fo rward voltage v gs = 0 v, i s = 9.0 a -- -- 1.5 v t rr reverse recovery time v gs = 0 v, i s = 11.6 a, di f / dt = 100 a/ s -- 128 -- ns q rr reverse recovery charge -- 0.56 -- c FQD12N20LTM_f085 rev. b 2 www.fairchildsemi.com
fqd12n20 ltm_f085 200v logic level n-channel mosfet 0 5 10 15 20 25 30 0 2 4 6 8 10 12 v ds = 100v v ds = 40v v ds = 160v no te : i d = 11.6 a v gs , g ate-source voltage [v] q g , to tal gate charge [nc] 10 -1 10 0 10 1 0 300 600 900 1200 1500 1800 c iss = c gs + c gd (c ds = shor ted) c oss = c ds + c gd c rss = c gd no tes : 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capac itance [pf] v ds , d rain-source voltage [v] 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 10 -1 10 0 10 1 150 notes : 1. v gs = 0v 2. 250 s pulse test 25 i dr , r everse drain current [a] v sd , source-drain voltage [v] 0 6 12 18 24 30 36 0.0 0.3 0.6 0.9 1.2 1.5 v gs = 5 v v gs = 10v r ds (on) [ ? ], dr ain-source on-resistance i d , drain current [a] 02468 10 10 -1 10 0 10 1 150 25 -55 notes : 1. v ds = 30 v 2. 250 s pulse test i d , d rain current [a] v gs , g ate-source voltage [v] 10 -1 10 0 10 1 10 -1 10 0 10 1 v gs top : 10 v 8.0 v 6.0 v 5.0 v 4.5 v 4.0 v 3.5 v bottom : 3.0 v not es : 1. 250 s pulse test 2. t c = 25 i d , drain current [a] v ds , drain-source voltage [v] typical characteristics figur e 5. capacitance characteristics figure 6. gate charge characteristics figure 3. on-resistance variation vs. drain current and gate voltage figure 4. body diode forward voltage variation vs. source current and temperature figure 2. transfer characteristics figure 1. on-region characteristics FQD12N20LTM_f085 rev. a 3 www.fairchildsemi.com FQD12N20LTM_f085 rev. b 3 www.fairchildsemi.com
fqd12n20 ltm_f085 200v logic level n-channel mosfet 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 -1 10 0 n o te s : 1. z jc (t) = 2.27 /w m ax. 2. d u ty f actor, d =t 1 /t 2 3 . t jm - t c = p dm * z jc (t) si ngle pulse d=0 .5 0.0 2 0.2 0.0 5 0.1 0.0 1 z jc (t), therm al response t 1 , s q u are w ave p u lse d ura tion [sec] 25 50 75 100 125 150 0.0 1. 5 3.0 4.5 6.0 7.5 9.0 i d , dr ain current [a] t c , c ase temperature [ ] 10 0 10 1 10 2 10 -1 10 0 10 1 10 2 10 s dc 10 ms 1 ms 100 s ope ration in this area is limited by r ds( on) not es : 1. t c = 25 o c 2 . t j = 1 5 0 o c 3 . single pulse i d , d rain current [a] v ds , d rain-source voltage [v] -10 0 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 n o tes : 1. v gs = 10 v 2 . i d = 5.8 a r ds( on) , ( normalized) drain-source on-resistance t j , j unction temperature [ o c] -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 not es : 1. v gs = 0 v 2. i d = 250 a bv dss , (n ormalized) drain-source breakdown voltage t j , j unction temperature [ o c] typical characteristics (continued) fi gure 9. maximum safe operating area figure 10. maximum drain current vs. case temperature figure 7. breakdown voltage variation vs. temperature figure 8. on-resistance variation vs. temperature figure 11. transient thermal response curve t 1 p dm t 2 FQD12N20LTM_f085 rev. b 4 www.fairchildsemi.com
fqd12n20 ltm_f085 200v logic level n-channel mosfet typical characteristics FQD12N20LTM_f085 rev. a 3 www.fairchildsemi.com FQD12N20LTM_f085 rev. b 5 www.fairchildsemi.com figure 12. u n c l a m p e d i n d u c t i v e switching capability 0. 001 0.01 0.1 1 10 1 10 20 sta rting t j = 12 5 o c sta rting t j = 25 o c i as , av alanche current (a) t av , tim e in avalanche (ms) t av = (l)(i as )/( 1.3*rated bv dss - v dd ) if r = 0 if r 0 t av = (l/r)ln[(i as *r)/(1.3*rated bv dss - v dd ) +1]
fqd12n20 l tm_f085 200v logic level n-channel mosfet cha rge v gs 5v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut cha rge v gs 5v q g q gs q gd 3ma v gs dut v ds 300nf 50k 200nf 12v same type as dut v gs v ds 10% 90% t d(o n) t r t on t off t d(o ff) t f v dd 5v v ds r l dut r g v gs v gs v ds 10% 90% t d(o n) t r t on t off t d(o ff) t f v dd 5v v ds r l dut r g v gs ga te charge test circuit & waveform resistive switching test circuit & waveforms FQD12N20LTM_f085 rev. b 6 www.fairchildsemi.com
fqd12n20 l tm_f085 200v logic level n-channel mosfet peak d iode recovery dv/dt test circuit & waveforms dut v ds + _ driv er r g sam e type as dut v gs d v/dt controlled by r g i sd con trolled by pulse period v dd l i sd 10v v gs ( d river ) i sd ( dut ) v ds ( dut ) v dd bo dy diode forward voltage drop v sd i fm , b ody diode forward current body diode reverse current i rm bo dy diode recovery dv/dt di/ dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driv er r g sam e type as dut v gs d v/dt controlled by r g i sd con trolled by pulse period v dd l l i sd 10v v gs ( d river ) i sd ( dut ) v ds ( dut ) v dd bo dy diode forward voltage drop v sd i fm , b ody diode forward current body diode reverse current i rm bo dy diode recovery dv/dt di/ dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period -------------------------- FQD12N20LTM_f085 rev. b 7 www.fairchildsemi.com
fqd12n20 ltm_f085 200v logic level n-channel mosfet pac kage dimensions 6.60 0.20 2.30 0.10 0.50 0.10 5.34 0.30 0.70 0.20 0.60 0.20 0.80 0.20 9.50 0.30 6.10 0.20 2.70 0.20 9.50 0.30 6.10 0.20 2.70 0.20 min0.55 0.76 0.10 0.50 0.10 1.02 0.20 2.30 0.20 6.60 0.20 0.76 0.10 (5.34) (1.50) (2xr0.25) (5.04) 0.89 0.10 (0.10) (3.05) (1.00) (0.90) (0.70) 0.91 0.10 2.30typ [2.300.20] 2.30typ [2.300.20] max0.96 (4.34) (0.50) (0.50) dpak FQD12N20LTM_f085 rev. b 8 www.fairchildsemi.com
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-6 supersot ? -8 supremos ? syncfet ? sync-lock? ? * the power franchise ? tinyboost ? tinybuck ? tinycalc ? tinylogic ? tinyopto ? tinypower ? tinypwm ? tinywire ? trifault detect ? truecurrent ? * serdes ? uhc ? ultra frfet ? unifet ? vcx ? visualmax ? xs? * trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized for use as critical co mponents in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provi ded in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. anti-counterfeiting policy fairchild semiconductor corporation's anti-counterfeiting policy. fairchild's anti-counterfeiting policy is also stated on our external website, www.fairchildsemi.com, under sales support. counterfeiting of semiconductor parts is a growing problem in t he industry. all manufacturers of semiconductor products are exp eriencing counterfeiting of their parts. customers who inadvertently purchase counter feit parts experience many problems such as loss of brand reputation, substandard p erformance, failed applications, and increased cost of production and manufacturing delays. fairchild is taking strong measures to protect ourselves and our cus tomers from the proliferation of counterfeit parts. fairchild strongly encourages customers to purchase fairchild parts eit her directly from fairchild or from a uthorized fairchild distributors who are listed by country on our web page cited above. products customers buy either from fairchild directly or from authorized fairchi ld distributors are genuine parts, have full traceability, meet fairch ild's quality standards for handling and storage and pr ovide access to fair child's full range of up-to-date technical and product information. fairchild and our authorized distributors will stand behind all warranties and will appropr iately address any warranty issues t hat may arise. fairchild will not provide any warranty coverage or other assistance for parts bought from u nauthorized sources. fairchild is committed to combat this glo bal problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. product status definitions definition of terms datasheet identification product status definition advance information formative / in design datasheet contains the design s pecifications for product developmen t. specifications may change in any manner without notice. preliminary first production datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production datasheet contains final specific ations. fairchild semiconductor reserves the right to make changes at any time without notice to improve the design. obsolete not in production datasheet contains specificati ons on a product that is disconti nued by fairchild semiconductor. the datasheet is for reference information only. rev. i48 fqd12n20 l tm_f085 200v logic level n-channel mosfet FQD12N20LTM_f085 rev. b 9 www.fairchildsemi.com
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